In conventional photolithographic processing, integrated circuits are created on a semiconductor wafer by exposing the wafer with a pattern of features on a mask or reticle. The pattern of features selectively exposes photosensitive chemicals on a wafer that is then further chemically and mechanically processed to build up layers of the integrated circuit.
As the features on a mask become smaller and smaller, optical distortions can occur whereby the exposure pattern created on a wafer will not match the pattern of features on the mask. To correct this, numerous resolution enhancement techniques (RETs) may be employed to improve the image quality so that the exposure pattern on a wafer more faithfully matches the pattern of features desired. Such RETs often comprise making extensive changes to the corresponding pattern of features on a mask to compensate for the known distortions in the imaging process.
With conventional resolution enhancement techniques, data for a pattern of mask features are analyzed with a computer program to estimate how a corresponding pattern of features will print on a mask. The data for the individual mask features or portions thereof may be adjusted such that the pattern created on the wafer will more faithfully match the desired layout. In addition, features, such as subresolution assist features (SRAFs), may be added to the layout data as necessary to improve printing fidelity. Typically, SRAFs are rectangular elements that are positioned adjacent to an edge of a feature in order to improve the contrast of the feature. The shape, size and placement of the SRAFs are typically predetermined, and often follow simple geometric rules.
While conventional resolution enhancement techniques are functional at compensating for some process distortions, a better match between the image produced and the image desired can be achieved.